DeepSeek V4 Flash on a Single AMD MI300X

DeepSeek V4 Flash on a single AMD MI300X This repository contains the configuration and patches I use to run deepseek-ai/DeepSeek-V4-Flash-0731 on one AMD MI300X in production. It includes the Docker Compose stack, SHA-256-pinned file overlays, reference diffs against upstream, and tuning tables. The checkpoint runs as shipped, without additional weight quantization or offload. Results from the pinned stack (vLLM ROCm nightly 0.26.1rc1.dev229+g124154a88.rocm723, AITER 0.1.19): Metric Result Single-stream decode (median per-stream, DSpark-7) 168.6 tok/s Prefill with tuned kernels ≈ 7.9–8.5K tok/s (6,988–7,019 tok/s on fresh prompts in the shipping profile) 8 concurrent streams 542 tok/s aggregate, 90.3 tok/s median per stream 64-stream burst 830 tok/s aggregate, no OOM, no engine errors Context 256K validated (the architecture supports 1M) Weights in HBM 156.67 GiB — no additional quantization or weight offload The official vLLM recipe targets NVIDIA and newer AMD hardware. Running the model reliably on MI300X required fixes for its FP8 format, MoE routing at high concurrency, causal speculative verification, CPU-KV synchronization, and several untuned kernel shapes. This repository collects those fixes and pins the versions used in production. Why MI300X The MI300X has 192 GB of HBM3 and 5.3 TB/s of memory bandwidth, with 2.4× the HBM capacity of an H100 SXM5 (AMD). Doubleword's write-up estimates that it costs roughly half as much at list price. For this 304B-parameter checkpoint, the memory capacity allows a simple single-GPU deployment: The entire model fits in HBM without PCIe weight streaming or layer offload. There is room for a 20 GB GPU KV pool and a 96 GiB CPU tier for evicted prefix-cache entries. One card handles 2–8 typical concurrent streams and bursts of up to 64 streams. MI300X (CDNA3) implements the AMD/Graphcore fnuz variant of E4M3, while MI325X and newer use OCP-standard FP8 (background). A kernel that assumes OCP semantics on MI300X can be wrong by a factor of two in the scale domain. Correctness on this FP8 implementation was the first priority; performance tuning came afterward. Prior art, and what this repo adds Fergus Finn's MI300X worklog and the accompanying Doubleword repository identified the FP8 incompatibility, missing AITER fast paths on gfx942, HIP-graph hazards in sparse MLA decode, and MoE routing bugs. The official vLLM recipe covers NVIDIA hardware and newer AMD GPUs (MI325X at 4K context and MI355X), but not a single-MI300X production configuration for the 0731 checkpoint. This repository adds: Correctness overlays for the pinned ROCm nightly, including fixes not yet in upstream vLLM. A validated serving configuration with probabilistic DSpark drafting, block rejection, and static K=7. It uses a 2,048-token scheduler budget and a 1,024-token long-prefill cap to prevent a cold prompt from stalling other streams. AITER GEMM tuning tables for the recurring gfx942 shapes the packaged tables were missing, plus a gfx942 OGS geometry override for the MXFP4 experts. A hybrid KV strategy: 20 GB of fp8_ds_mla GPU cache + 96 GiB native CPU offload, with a load-path fencing fix that upstream issue #47282 documents but PR #47291 never merged. Repository layout . ├── compose.yaml # The production stack (vLLM ROCm + Caddy), digest-pinned ├── Caddyfile.example # Copy to Caddyfile; set hostname, email, and source CIDR ├── vllm-entrypoint.sh # Removes stale CPU-KV mmaps from /dev/shm before start ├── SHA256SUMS # SHA-256 pins for every runtime artifact ├── patches/ │ ├── *.py # Byte-for-byte production overlays (mounted read-only) │ ├── diffs/*.patch # Unified diffs vs. the upstream base revision │ └── README.md # Provenance and regeneration instructions └── tuning/ └── *.csv # AITER A8W8 blockscale tuning tables for gfx942 Runtime configuration The stack uses a digest-pinned official vLLM ROCm nightly with: --trust-remo